A cell size in a resistive memory is limited by a controller FET or the memory element itself, where sizes are scaled with minimum feature size F in a technology node. A unit area for placing the memory element includes the element and space in-between surrounding elements. The area of the unit can be reduced down to 4 F2. On the other hand an access/controller transistor unit using a planer FET is limited down to 8 F2, as found in experience with DRAM fabrication. Use of 3D FETs is necessary to downsize the memory cell below 8 F2.
Considering an oval memory element with an aspect ratio r, dimensions of long and short axes are assumed as rF and F as shown in FIG. 1A, which illustrates a top view. The most packed placement of the memory element is when disposed with minimum space F. Dimensions (pitches) of the placement in both directions, (r+1)F and 2 F define a unit area as 2(r+1)F2, and in particular it becomes 4 F2 when the memory element is a circle or square in a top view.
Placement of the access transistor also dominates cell size. Minimum pitch in channel width direction is 2 F as line and space of active area 1 F+isolation area 1 F. In channel direction 4 F is at least required as ½ F of isolation, 1 F of contact, 1 F of gate, ½ F of common source and 1 F (i.e. ½ F×2) of contact margin as shown in FIG. 1B. The minimum cell size never gets lower than 2 F×4 F=8 F2 as long as a planar transistor is used.
A vertical channel transistor can be a solution to break through the 8 F2 area size wall. H. Sunami teaches various applications using a surround gate transistor (SGT), in U.S. Pat. No. 6,373,099. By using a silicon pillar surrounded by a cylindrical gate and forming a vertical channel, the unit size can be scaled down to 4 F2. There however are remaining issues to be solved in practice such as the features of a word line, a source line, a contact, and their fabrication process. The surrounding gate is fabricated on the sidewall of the pillar built in silicon substrate. A word line connects individual gates in one direction to make it work as a memory array. A mask process would be required to fabricate the word line, which faces two serious challenges of performing photolithography over a non-planarized surface and misalignment to the pillars. Fine lithography requires a flat surface. In addition there is no room left to allow misalignment since the distance between the transistors is assumed as 1 F.
Furthermore, the source element of the surrounding gate is defined by ion implantation. The whole area other than the surrounding gate is implanted. It is also hard to separate the source into individual source lines. Thus, it would not work other than for a plate source. It is also difficult to lower the resistance enough to maintain applied voltage. Voltage bouncing or propagation delay is a serious concern.
The present invention provides miniaturized resistive memory cells down to 4 F2 with solutions for above issues.